1. Field of the Invention
The present invention relates to an integrated circuit having a function for enabling a mode of a circuit to be switched over if a predetermined signal is input to a mode switching signal input terminal in a condition where a predetermined voltage is applied to one or more signal input terminals.
2. Prior Art and Related Reference
In a conventional integrated circuit, (1) a semiconductor device is described in, for example, Japanese Patent Application Laid-Open No. 1990-278171 published on Nov. 14, 1990 in Japan. A test terminal, a test circuit, and a resistive element are provided for the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 1990-278171. The semiconductor device has the test circuit serving as the resistive element between an input terminal and a power source. Further, the semiconductor device is fundamentally constructed as will be later described and as shown in FIG. 1. With reference to FIG. 1, reference numerals 11, 13, and 14 correspond to the input terminal, an input stage transistor, and the test terminal, respectively.
The test terminal is pulled up by a pull-up resistive element 15. Reference numeral 12 refers to the test circuit which includes a single transistor having a large ON resistance.
The test circuit 12 is turned OFF if the test terminal 14 is opened or a high voltage is applied to the test terminal 14. On the other hand, the test circuit 12 is turned ON if a low voltage is applied to the test terminal 14. When the test circuit 12 is held ON, the test circuit 12 serves as the resistive element because the test circuit 12 includes the transistor having the large ON resistance. Therefore, the resistive element is disposed between the input terminal 11 and the positive power source to connect with each other so that the input terminal 11 is pulled up. Thus far, a description has been made for a case where the input terminal 11 is pulled up by the test circuit 12. However, with the test circuit 22 as will be described later and as shown in FIG. 2, the input terminal 21 may be pulled down. In this case, when the high voltage is applied to the test terminal 24, the input terminal 21 can be pulled down.
(2) On the other hand, the conventional semiconductor device constructed as shown in FIG. 3 is also well known in the art. Reference numeral 30 in FIG. 3 refers to an essential component circuit in an integrated circuit .beta.. In this figure, terminals of an integrated circuit 30 are partially illustrated. A test mode setting terminal A serves as a terminal to input a voltage signal required for turning ON and OFF a test mode setting logic circuit 32. Signal terminals B1, B2, B3 serve as terminals to input and output a signal, and serve as terminals to set and input a voltage level which is required during the test mode.
In the integrated circuit 30, when a ground voltage (GND) is applied to the test mode setting terminal A, the test mode setting logic circuit 32 is switched over to the test mode. Accordingly, it is possible to test in the condition that the signal terminal B1 is set to a power source voltage Vcc, that the signal voltage B2 is set to the ground voltage, and that the signal terminal B3 is set to any reference voltage V.sub.E. Additionally, the integrated circuit 30 leaves the test mode when the test mode setting terminal A is set to the power source voltage Vcc or is opened.
However, in the semiconductor device as disclosed in Japanese Patent Application Laid-Open No. 1990-278171, the integrated circuit can exit the test mode only when the input terminal is opened. There is a further disadvantage in the semiconductor device as disclosed in Japanese Patent Application Laid-Open No. 1990-278171. Namely, the semiconductor device cannot include two or more of each circuit to set the terminal voltage to the power source voltage Vcc, to the ground voltage (GND) or to an optional voltage, respectively. Furthermore, to activate a plurality of integrated circuits .beta. as shown in FIG. 3 in the test mode simultaneously, the respective integrated circuits .beta. should be arranged as shown in FIG. 4. That is, it is necessary to connect the signal input terminals B1 to B3 with each other as well as the test mode setting terminals A. Thus, increasing the number of the integrated circuits .beta. causes a complicated wiring, and requires vast amount of labor and time. In addition, some terminals cannot be possibly wired due to a restricted dimension of a package or a limited space in circumference.
If the integrated circuit .beta. is aged in the test mode, fundamental circuits become aged while some circuit blocks are not aged. For example, it is impossible to age the logic circuit 31 disposed between the signal input terminals B1 to B3 and the test mode setting terminal A. The logic circuit 31 can be activated in any mode other than the test mode. As a result, there is another drawback that the whole circuit may not provide a high reliability.